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    2. synplicity教程

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      上传日期: 2006-03-27

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      synplicity教程:ObjecTIve: becoming familiar with basic features of Synplify using the Synplify GUI
      After compleTIng this lab, the user will be able to:
      • Build a  project: include all the HDL source files for the design, select the target
      architecture and opTIons, compile, and synthesize the design.
      • Understand the log file: become familiar with the various secTIons and useful information reported in the log file.
      • Use HDL analyst: analyze the HDL source code, inspect the RTL and the mapped schematics, and cross-probe between RTL & technology schematics and the source code.
      Build a project, add & compile the HDL source files, and synthesize the design
      1. Invoke Synplify
      2. Create a new project a. File -> New -> Project File
      Or click on the quick access button “P”
      3. Add HDL source files
       a. Source -> Add Source Files
        Or click on the quick access button “ADD”
      b. Go to synplify_labs\lab1\verilog or vhdl
      c. Select alu.v (alu.vhd) and Hdl_demo.v (Hdl_demo.vhd) & click on open
      Note:  Make sure that HDL_demo.v/HDL_demo.vhd (top level) is the last file in the list since Synplify picks the last module as the top level module for VERIOG/VHDL designs.
      4. Select the target architecture and options
      a. Target  -> Set Device Options
      Select the following options in the Set Device Options pop-up window:
      Technology: Actel 42MX
      Part:  42MX09
      Speed Grade: Std
      Fanout Guide: 16
      Note: Your choices are displayed under the “Target ” area in Synplify’s project window.


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